looks like in #SystemVerilog when you prefix a task's argument with "ref", the parser thinks all the following arguments are also references¹, a là declaring the arguments without specifying the type for each², so you have to make the references the last arguments and call the task with (x, , z) if there are optional arguments (with default values) in-between
the LRM doesn't seem to clearly specify this behavior
I don't like this language at all, and I don't understand why people even prefer it

¹ i.e. (ref first_t a, second_t b) is the same as (ref first_t a, ref second_t b)
² where (first_t a, b) is the same as (first_t a, first_t b)

today in my #SystemVerilog and #UVM adventures I realised that
- static class members (properties and methods) are incompatible with parametric classes, and I'd prefer to keep the latter
- there should be a way to wrap many parameters into one structure, resolved at compile time — like a record/struct but made of types and constants, that would be nice

for #SystemRDL and similar languages there are (synthesisable) register block generators, having #AXI or AXI Lite on one end and a bunch on signals corresponding to the fields on another
similar generated blocks for parsing and forming AXI Stream should be a thing as well, turning an octet stream into a structure together with a validity and no-longer-needed signals, or vice versa

#HDL #VHDL #SystemVerilog #Verilog #HLS

just stumbled upon this #SystemVerilog construct

class foo #(BASE = type) extends BASE;

and I can't decide if it's clever or obnoxious

BTW is this possible in C++, making a class template parametrised by another class which the class is inherited from

so far there's just one thing that drives me mad about #VHDL, or maybe specifically it's implementation in #Vivado:
if I name a component not exactly as the entity and forget to add corresponding configuration, it simply won't create the instance in the architecture and won't connect the signal, and issue no error whatsoever, just silently continue as if nothing happened
and then if I add the configuration, it still refuses to pick it up and doesn't create the instance
this ought to be a bug, should try it on #GHDL perhaps

in other respects it's pretty nice to write in, at first there are more, sometimes silly, errors (like you have gazillion of types which all are essentially a bit vector¹, and the type-checker will fuck with you if you aren't properly converting one into the other), and there are much fewer syntactic constructs than in #Verilog, let alone #SystemVerilog, that you're forced to wrap it all properly, but then, if it works, it works correctly, the way you intended
I pretty much want to try and use #Ada for a firmware, and I don't care if the tool-chain is proprietary (is #GNAT proprietary?) — the FLOSS enthusiasts should adopt better standards if they want me to use their stuff and contribute more

¹ boolean, bit, std_logic for single bit; arrays thereof; std_logic_vector, signed, unsigned, integer, natural, positive, time, and real are all mutually incompatible, modulo few exceptions
if-then-else only works with booleans, you can't just put a value of std_logic in place of the condition

#OSVVM looks pretty nice, modulo the naming convention which is kinda cringe, unlike #UVM it does really contain actual helpful utilities, not just a standardised interface

#FPGA #ASIC #VHDL #SystemVerilog #Verilog

I still don't understand how delta-sigma modulation really works, what makes the pulses evenly distributed in time and not just lumped together as in pulse-width modulation
but I guess I've just found an algorithm for producing that same pattern without any feedback loops

we have
- a register with the desired value of pulses density, but the bits are in reverse order (LSB on the left)
- a counter, same width as the register, incremented on every clock cycle, overflowing without restrictions
- a combinatorial function deciding whether the output is high or low depending on the values in the registers

the combinatorial function
- determines by what power of two the counter is divisible in this clock cycle (where's the first 1, counting from LSB)
- the output is the value of the bit in corresponding position of the reversed register holding the density
- basically chained ("horizontal") OR of the counter, in every position AND NOT'd with the neighbouring bit, that's the mask to apply to the density register and then compare the result to zero

it's essentially like PWM but smoother
e.g. if the MSB of the density is high (the value in it is at least 1/2), every second clock cycle there will be a pulse
and if the LSB of the density is high (the value in it odd), one of the pulses will only be present in second half of the 2^width period

p.s. you can make the period be filled with up to 2^width-1 pulses, one will always be zero (the very first one corresponding to counter = 0)

#FPGA #ASIC #VHDL #SystemVerilog #Verilog

they always say in digital electronics you only have zeros and ones — not quite: if you describe a differential line as a bit-vector of two elements, it's valid states are (0, 1) and (1, 0), the waveform viewer will show it to you as 1 and 2 respectively
speaking of differential lines, the often mentioned reason for their use is better noise tolerance, so you can use lower voltage for transmission and detect the signal with an opamp having the inverting and non-inverting inputs connected to the two wires
another reason why you might want to use differential signal internally is to avoid negation (extra inverters) at the expense of more wiring — each inverter on the signal's path adds a tiny but still extra delay and you might want to reduce that as much as possible if the path is critical enough

#FPGA #ASIC #VHDL #SystemVerilog #Verilog

today I was wondering about how I'd describe a ring oscillator or a delay made of chained inverters in typical #VHDL or #SystemVerilog — that's not possible, AFAICT: the synthesiser will just optimise out the double negations by the LEM — and what should I use instead
also noticed that ternary arithmetic might come in handy to describe a signal which may be 0, 1, or -1, e.g. the output of a phase frequency detector or some other digital circuit where the high voltage may be as positive as negative — VHDL might accommodate that just fine as just another library

the testbench for this project is going to be in #SystemVerilog + #UVM anyway (that's what I know), but the designs themselves are partly #VHDL and I'm not only not going to change the fact but also write new modules in it instead of SV

any sufficiently advanced verification model is indistinguishable from full-blown operating system
I actually haven't made my mind if #SystemC is good idea or not: compared to #SystemVerilog, C++'s complexity is not there

today I've apparently found a bug in #Vivado — due to a combination of an interface with inout ports, driven from a class within the interface, which then gets overloaded by reassigning type value in a static property of another class (factory), the interface itself gets passed to module, then the values of a signal sampled on posedge within the module and outside of it became different and broke (AXI) handshaking
guess AMD should hire me already

the model I used was total shit just waiting to stab me in the back, I just couldn't find anything better and wanted to avoid implementing even AXI Lite by myself, then I searched again and found #TVIP #AXI which seems pretty solid so far

https://github.com/taichi-ishitani/tvip-axi

#Verilog #SystemVerilog