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#hbm4

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JEDEC Approaches Finalization of #HBM4 Standard, Eyes Future Innovations

HBM4 is set to introduce a doubled channel count per stack compared to HBM3, with a larger physical footprint

HBM4 will specify 24 Gb and 32 Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks

The committee has initial agreement on speeds bins up to 6.4 Gbps with discussion ongoing for higher frequencies

jedec.org/news/pressreleases/j

www.jedec.orgJEDEC Approaches Finalization of HBM4 Standard, Eyes Future Innovations | JEDEC

#HBM4 to double speeds in 2026 — 2048-bit interface to revolutionize #AI and #HPC markets

Trendforce reports that HBM4 will significantly depart from traditional standardized DRAM technologies to more customized solutions

HBM4 will mark the first use of a 12nm process wafer for its bottommost logic die, to be supplied by foundries

HBM4 is set to expand from the current 12-layer (12hi) to 16-layer (16hi) stacks, spurring demand for new hybrid bonding techniques

tomshardware.com/pc-components

Tom's Hardware · HBM4 memory to double speeds in 2026 — 2048-bit interface to revolutionize artificial intelligence and HPC markets: ReportBy Anton Shilov

SK hynix & Nvidia reportedly working on a #GPU redesign that 3D-stacks #HBM4 directly on top of the processing cores, eliminating interposers

This resembles AMD's 3D V-Cache, which is placed directly on CPU dies, but HBM will be bigger capacity & cheaper, albeit slower

tomshardware.com/news/sk-hynix

Tom's Hardware · SK Hynix and Nvidia reportedly working on a radical GPU redesign that 3D-stacks HBM memory directly on top of the processing coresBy Anton Shilov