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#ecp5

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I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain.

blog.bomorgan.io/hobbies/hardw

#riscv#foss#fpga

AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)

You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).

github.com/YosysHQ/nextpnr/iss
#verilog #fpga #ncl #asynclogic

GitHubSegfault/exception on combinatorial looping design · Issue #1194 · YosysHQ/nextpnrBy tommythorn