Pro tips when using Migen's SyncFIFO() module in your pipeline design...
I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`
It helped a lot for timing closure of the design :)
Pro tips when using Migen's SyncFIFO() module in your pipeline design...
I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`
It helped a lot for timing closure of the design :)
I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.
I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain.
https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/
The 50€ #olimex #Gatemate board is a great value.
https://www.olimex.com/Products/FPGA/GateMate/
The extension boards make it a very viable choice.
https://github.com/intergalaktik/Extension_Boards_for_Olimex_GateMate
@olimex #fpga #ECP5 #pico-ice
@BrunoLevy01 I have several #FPGA boards here. Three of them have an #ICE40 FPGA, three of them are Xilinx-based, and the last is the #ECP5 evaluation board with an ECP5-5G 85F. Which do you recommend for your FPGA tutorial series? Thank you!
AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)
You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).
https://github.com/YosysHQ/nextpnr/issues/1194#issuecomment-1684724413
#verilog #fpga #ncl #asynclogic