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#cpczero

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Bread80<p>Adding basic 6502 emulation to my gate level logic simulator for the CPC ZERO project. I'm only adding emulation of the various cycle types to validate the rest of the system. Here it's raising an error because the RESET pulse is shorter than the 6502 requires.</p><p><a href="https://mstdn.social/tags/Amstrad" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Amstrad</span></a> <a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a> <a href="https://mstdn.social/tags/Kicad" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Kicad</span></a> <a href="https://mstdn.social/tags/Delphi" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Delphi</span></a></p>
Bread80<p>The CPC ZERO project has been stalled pending some updates to my gate level simulator. I needed it to be able to handle gate delays so I could properly test the sequencer circuit. Today I've been adding necessary code. All the timing data is currently hard coded into the simulator, rather than loaded from a file, but that's enough for now.</p><p>I found the circuit was starting with the shift registers out of phase but a tweak to the reset circuit appears to have fixed things.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a> <a href="https://mstdn.social/tags/AmstradCPC" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>AmstradCPC</span></a></p>
Bread80<p>Pixel generation is a lot more fun to work on. It requires parallel in, parallel out shift registers. I thought they'd be difficult to find but the 74LS164 is still available. It can even shift either direction but I don't need that functionality.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>I needed to do something calming today. Entering schematics is often calming. So I been working on the DRAMs and multiplexers. But doing everything eight times is not the calming I was looking for.</p><p>I still have to assign address lines to DRAM pins but that will depend on board layout so I'll leave for later. The same for address lines to the multiplexers. That requires more concentration than I can muster today.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>A rework of the sequencer circuit. I was using the state of the shift registers to inject the initial 1 pulse into the shift registers. However the LS164s are too slow for that to work. That meant the two shift registers might start up out of phase.</p><p>I've added a fast 74S74 to generate a reset pulse from /RESET and 16MHZ to guaranteed the phasing. But the sequencer needs to generate CPU clocks during reset, so a second S74 acts as an edge detects ~RESET down to a single 16MHz cycle.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>And the project file so far for the CPC ZERO.</p><p>The CAD files don't give enough detail on the oscillator so this needs to be specified in the project file with the AddOscillator command which has parameters for name, frequency and the net to drive.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a> <a href="https://mstdn.social/tags/Smorgasbord" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Smorgasbord</span></a></p>
Bread80<p>Playing with sequencer circuits in Logisim Evolution. This looks like it's doing the job.</p><p>For memory control I need to trigger actions on both the rising and falling edge of the 16MHz system clock. So I'm using two shift registers, one clocked on the rising edge and one on the falling edge.</p><p>It's then a case of gating signals off the eight possible steps. Flip-flips drive the video vs CPU selector (the 2MHz CPU clock), the 1MHz CRTC clock, and gate CAS.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>Doing some testing on the CPC ZERO. I’ve coded a loop which takes 9 clocks and includes one write cycle. I found a few bad solder joints on the lines between the ROM ZIF socket and its header pins.</p><p>After resoldering them I now get the output below. Yellow is clock, blue is R/W. However it’s easy to knock it off course into what looks like constantly retriggering BRK cycles (unused memory addresses are filled with $00, the BRK opcode).</p><p>Hopefully better power input will fix this.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>Boning up on the 6502 boot sequence and realising I need to change the memory map slightly. I was going to put video memory from C000 to FFFF but that won’t play nicely with the interrupt vectors.</p><p>The best solution looks to be putting video memory between 8000 and BFFF. The downside is how this splits available RAM.</p><p>IO can slide up from the page at BF00 to C000.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>Prepping for the next stage on the CPC ZERO. New sockets and header added.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>Using Logisim Evolution to validate (and fix) some circuits for the CPC ZERO.</p><p>I haven't used Logisim for a could of years but it's now feeling very solid and user friendly. I'd highly recommend it.</p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a></p>
Bread80<p>The first stage of my CPC ZERO build - a hypothetical 6502 based Amstrad CPC taking inspiration from the prototype 6502 board and the final Z80 based CPC464.</p><p>I'm using period appropriate hardware, wire wrapping the build, and solving design challenges the way they had to in the eighties.</p><p>In this zero-th part I state my design goals, choose a build method and build out the CPU and ROM.</p><p><a href="https://bread80.com/2024/11/01/cpc-zero-part-0-intro-cpu-and-rom/" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">bread80.com/2024/11/01/cpc-zer</span><span class="invisible">o-part-0-intro-cpu-and-rom/</span></a></p><p><a href="https://mstdn.social/tags/CPCZERO" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CPCZERO</span></a> <a href="https://mstdn.social/tags/Amstrad" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Amstrad</span></a> <a href="https://mstdn.social/tags/MOS6502" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>MOS6502</span></a> <a href="https://mstdn.social/tags/WireWrapping" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>WireWrapping</span></a></p>
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